Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices (e.g., NAND, NOR, etc.) have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data values for some extended period without the application of power. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the memory cells, through programming (which is sometimes referred to as writing) of charge-storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each memory cell. Common uses for flash memory and other non-volatile memory may include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
In a NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a data line, such as a bit line. A “column” refers to a group of memory cells that are commonly coupled to a local data line, such as a local bit line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line.
Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, e.g., source to drain, between a pair of select lines, e.g., a source select line and a drain select line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. Each source select gate is connected to a source line, while each drain select gate is connected to a data line, such as column bit line.
Data lines are sometimes coupled to circuitry that may be configured to handle relatively low voltages (e.g., that may be referred to as low-voltage circuitry), such as data cache circuitry. The low-voltage circuitry may provide relatively low voltages (e.g., 0 (zero) V up to about 4 V) to the data lines during read or write operations.
However, during erase operations (e.g., involving NAND memory arrays), memory cells may be erased a block at a time by grounding all of the access lines in the block, for example, while allowing the data lines to float. A relatively high erase voltage (e.g., about 20 to 30 V) is then applied to a semiconductor on which the memory cells are formed, and thus to the channels of the memory cells, to remove the charge from the charge-storage structures. This can cause the data lines to float to about the erase voltage and can damage the low-voltage circuitry coupled to data lines.
Therefore, circuit-protection devices, such as field-effect transistors (FETs), may be coupled between the data lines and the low-voltage circuitry for protecting the low-voltage circuitry from the relatively high voltages that may be present on the data lines during an erase operation. The circuit-protection devices may be coupled on a one-to-one basis to the data lines or one circuit-protection device to two or more data lines through a multiplexer. However, the pitch of the circuit-protection devices may be relatively large in order to avoid breakdown of the circuit-protection devices. For example, the relatively large pitch uses up considerable area and thus may increase the size of the memory device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative circuit-protection devices that allow for smaller pitches.